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SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences


Jun 29, 2022
Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo

* Accepted by 59th DAC 

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PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs


Jan 25, 2022
Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian

* Preprint of the paper to be published in Design, Automation and Test in Europe Conference (DATE 2022) 

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FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications


Jul 01, 2020
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen

* IEEE International Conference on Field Programmable Logic and Applications (FPL), 2020 

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Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis


May 06, 2019
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

* Preprint: to appear in Proceedings of Design, Automation and Test in Europe (DATE 2019) 

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