Picture for Yichen Shen

Yichen Shen

Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications

Oct 06, 2020
Matthew Khoury, Rumen Dangovski, Longwu Ou, Preslav Nakov, Yichen Shen, Li Jing

Figure 1 for Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications

Figure 2 for Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications

Figure 3 for Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications

Figure 4 for Vector-Vector-Matrix Architecture: A Novel Hardware-Aware Framework for Low-Latency Inference in NLP Applications

* To appear at the 2020 Conference on Empirical Methods in Natural Language Processing (EMNLP '20), November 16-20, 2020, NMT, AI accelerators, co-design, TPU, OPU, 10 pages, 3 figures, 4 tables

Access Paper or Ask Questions

Tunable Efficient Unitary Neural Networks (EUNN) and their application to RNNs

Apr 03, 2017
Li Jing, Yichen Shen, Tena Dubček, John Peurifoy, Scott Skirlo, Yann LeCun, Max Tegmark, Marin Soljačić

Figure 1 for Tunable Efficient Unitary Neural Networks (EUNN) and their application to RNNs

Figure 2 for Tunable Efficient Unitary Neural Networks (EUNN) and their application to RNNs

Figure 3 for Tunable Efficient Unitary Neural Networks (EUNN) and their application to RNNs

Figure 4 for Tunable Efficient Unitary Neural Networks (EUNN) and their application to RNNs

* 9 pages, 4 figures

Access Paper or Ask Questions