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Michaela Blott
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults

Nov 11, 2020
Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees Vissers


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LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

Apr 06, 2020
Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott


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Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA

Mar 24, 2020
Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott

* To appear in GECCO 2020 Proceedings 
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Efficient Error-Tolerant Quantized Neural Network Accelerators

Dec 16, 2019
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees Vissers

* 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 
 * 6 pages, 5 figures 
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Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

Nov 21, 2018
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees Vissers, John Wawrzynek, Kurt Keutzer

* To appear in the 27th International Symposium on Field-Programmable Gate Arrays, February 2019 
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Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic

Jul 17, 2018
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Leong, Peter Y. K. Cheung

* Accepted by ARC 2018 
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FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs

Jul 11, 2018
Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott

* Accepted for publication, 28th International Conference on Field Programmable Logic and Applications (FPL), August, 2018, Dublin, Ireland 
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SYQ: Learning Symmetric Quantization For Efficient Deep Neural Networks

Jul 01, 2018
Julian Faraone, Nicholas Fraser, Michaela Blott, Philip H. W. Leong

* Published as a conference paper at the 2018 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) 
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Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

Jun 26, 2018
Michaela Blott, Thomas B. Preusser, Nicholas Fraser, Giulio Gambardella, Kenneth OBrien, Yaman Umuroglu, Miriam Leeser


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Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices

Jun 21, 2018
Thomas B. Preußer, Giulio Gambardella, Nicholas Fraser, Michaela Blott


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Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks

Oct 10, 2017
Julian Faraone, Nicholas Fraser, Giulio Gambardella, Michaela Blott, Philip H. W. Leong

* To appear as a conference paper at the 24th International Conference On Neural Information Processing (ICONIP 2017) 
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Scaling Binarized Neural Networks on Reconfigurable Logic

Jan 27, 2017
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers

* To appear in the PARMA-DITAM workshop at HiPEAC 2017, January 2017 
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FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Dec 01, 2016
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers

* To appear in the 25th International Symposium on Field-Programmable Gate Arrays, February 2017 
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