Picture for Haoxing Ren

Haoxing Ren

Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning

Add code
Jul 06, 2024
Viaarxiv icon

GOALPlace: Begin with the End in Mind

Add code
Jul 05, 2024
Viaarxiv icon

ILILT: Implicit Learning of Inverse Lithography Technologies

Add code
May 06, 2024
Viaarxiv icon

Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance

Add code
Apr 12, 2024
Figure 1 for Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
Figure 2 for Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
Figure 3 for Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
Figure 4 for Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
Viaarxiv icon

Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent

Add code
Feb 08, 2024
Viaarxiv icon

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation

Add code
Jan 19, 2024
Figure 1 for BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Figure 2 for BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Figure 3 for BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Figure 4 for BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Viaarxiv icon

ChipNeMo: Domain-Adapted LLMs for Chip Design

Add code
Nov 13, 2023
Figure 1 for ChipNeMo: Domain-Adapted LLMs for Chip Design
Figure 2 for ChipNeMo: Domain-Adapted LLMs for Chip Design
Figure 3 for ChipNeMo: Domain-Adapted LLMs for Chip Design
Figure 4 for ChipNeMo: Domain-Adapted LLMs for Chip Design
Viaarxiv icon

VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Add code
Sep 14, 2023
Figure 1 for VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Figure 2 for VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Figure 3 for VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Figure 4 for VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Viaarxiv icon

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design

Add code
Oct 27, 2022
Figure 1 for An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Figure 2 for An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Figure 3 for An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Figure 4 for An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Viaarxiv icon

TAG: Learning Circuit Spatial Embedding From Layouts

Add code
Sep 07, 2022
Figure 1 for TAG: Learning Circuit Spatial Embedding From Layouts
Figure 2 for TAG: Learning Circuit Spatial Embedding From Layouts
Figure 3 for TAG: Learning Circuit Spatial Embedding From Layouts
Figure 4 for TAG: Learning Circuit Spatial Embedding From Layouts
Viaarxiv icon