Alert button
Picture for Jeff Zhang

Jeff Zhang

Alert button

Harvard University

Advanced Language Model-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis

Add code
Bookmark button
Alert button
Dec 02, 2023
Kiran Thorat, Jiahui Zhao, Yaotian Liu, Hongwu Peng, Xi Xie, Bin Lei, Jeff Zhang, Caiwen Ding

Viaarxiv icon

Path Planning Under Uncertainty to Localize mmWave Sources

Add code
Bookmark button
Alert button
Mar 08, 2023
Kai Pfeiffer, Yuze Jia, Mingsheng Yin, Akshaj Kumar Veldanda, Yaqi Hu, Amee Trivedi, Jeff Zhang, Siddharth Garg, Elza Erkip, Sundeep Rangan, Ludovic Righetti

Figure 1 for Path Planning Under Uncertainty to Localize mmWave Sources
Figure 2 for Path Planning Under Uncertainty to Localize mmWave Sources
Figure 3 for Path Planning Under Uncertainty to Localize mmWave Sources
Figure 4 for Path Planning Under Uncertainty to Localize mmWave Sources
Viaarxiv icon

Millimeter Wave Wireless Assisted Robot Navigation with Link State Classification

Add code
Bookmark button
Alert button
Nov 05, 2021
Mingsheng Yin, Akshaj Veldanda, Amee Trivedi, Jeff Zhang, Kai Pfeiffer, Yaqi Hu, Siddharth Garg, Elza Erkip, Ludovic Righetti, Sundeep Rangan

Figure 1 for Millimeter Wave Wireless Assisted Robot Navigation with Link State Classification
Figure 2 for Millimeter Wave Wireless Assisted Robot Navigation with Link State Classification
Figure 3 for Millimeter Wave Wireless Assisted Robot Navigation with Link State Classification
Figure 4 for Millimeter Wave Wireless Assisted Robot Navigation with Link State Classification
Viaarxiv icon

RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance

Add code
Bookmark button
Alert button
May 22, 2021
Udit Gupta, Samuel Hsia, Jeff Zhang, Mark Wilkening, Javin Pombra, Hsien-Hsin S. Lee, Gu-Yeon Wei, Carole-Jean Wu, David Brooks

Figure 1 for RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance
Figure 2 for RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance
Figure 3 for RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance
Figure 4 for RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance
Viaarxiv icon

FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design

Add code
Bookmark button
Alert button
Jul 02, 2018
Jeff Zhang, Siddharth Garg

Figure 1 for FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
Figure 2 for FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
Figure 3 for FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
Figure 4 for FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
Viaarxiv icon

ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators

Add code
Bookmark button
Alert button
Mar 13, 2018
Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg

Figure 1 for ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
Figure 2 for ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
Figure 3 for ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
Figure 4 for ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
Viaarxiv icon

Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator

Add code
Bookmark button
Alert button
Feb 17, 2018
Jeff Zhang, Tianyu Gu, Kanad Basu, Siddharth Garg

Figure 1 for Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Figure 2 for Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Figure 3 for Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Figure 4 for Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Viaarxiv icon

Hierarchical Model for Long-term Video Prediction

Add code
Bookmark button
Alert button
Jul 03, 2017
Peter Wang, Zhongxia Yan, Jeff Zhang

Figure 1 for Hierarchical Model for Long-term Video Prediction
Figure 2 for Hierarchical Model for Long-term Video Prediction
Figure 3 for Hierarchical Model for Long-term Video Prediction
Figure 4 for Hierarchical Model for Long-term Video Prediction
Viaarxiv icon