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Brucek Khailany

ChipNeMo: Domain-Adapted LLMs for Chip Design

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Nov 13, 2023
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VerilogEval: Evaluating Large Language Models for Verilog Code Generation

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Sep 14, 2023
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HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression

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Nov 30, 2022
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An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design

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Oct 27, 2022
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Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training

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Jul 08, 2022
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Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training

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Jun 13, 2022
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Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks

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Mar 12, 2022
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GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement

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Mar 11, 2022
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NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

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Jul 09, 2021
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Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update

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Jun 26, 2021
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