Alert button
Picture for Yulhwa Kim

Yulhwa Kim

Alert button

L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ

Feb 15, 2024
Hyesung Jeon, Yulhwa Kim, Jae-joon Kim

Figure 1 for L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ
Figure 2 for L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ
Figure 3 for L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ
Figure 4 for L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ
Viaarxiv icon

SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks

Feb 14, 2024
Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim

Viaarxiv icon

Squeezing Large-Scale Diffusion Models for Mobile

Jul 03, 2023
Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim, Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon Kim, Hyungjun Kim

Figure 1 for Squeezing Large-Scale Diffusion Models for Mobile
Figure 2 for Squeezing Large-Scale Diffusion Models for Mobile
Figure 3 for Squeezing Large-Scale Diffusion Models for Mobile
Figure 4 for Squeezing Large-Scale Diffusion Models for Mobile
Viaarxiv icon

BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function

Mar 23, 2019
Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim

Figure 1 for BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function
Figure 2 for BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function
Figure 3 for BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function
Figure 4 for BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function
Viaarxiv icon

Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators

Nov 06, 2018
Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim

Figure 1 for Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
Figure 2 for Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
Figure 3 for Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
Figure 4 for Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
Viaarxiv icon