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Benchmarking TinyML Systems: Challenges and Direction

Mar 10, 2020
Colby R. Banbury, Vijay Janapa Reddi, Max Lam, William Fu, Amin Fazel, Jeremy Holleman, Xinyuan Huang, Robert Hurtado, David Kanter, Anton Lokhmotov, David Patterson, Danilo Pau, Jae-sun Seo, Jeff Sieracki, Urmish Thakker, Marian Verhelst, Poonam Yadav

* 5 pages, 1 figure, 2 tables 

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High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS

Sep 16, 2019
Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo


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Automatic Compiler Based FPGA Accelerator for CNN Training

Aug 15, 2019
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, Jae-sun Seo

* 6 pages, 9 figures, paper accepted at FPL2019 conference 

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FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning

Feb 27, 2019
Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas Kolala Venkataramanaiah, Jae-sun Seo, Matthew Mattina

* 10 pages, 8 figures, paper accepted at SysML2019 conference 

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Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain

May 23, 2018
Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings


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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression

Apr 19, 2018
Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo

* 2017 Asilomar Conference on Signals, Systems and Computers 

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Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations

Sep 19, 2017
Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo

* 2017 IEEE Biomedical Circuits and Systems (BioCAS) 

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Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs

Sep 29, 2016
R. Tapiador, A. Rios-Navarro, A. Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo

* 6 pages, 6 figures. Robotic and Technology of Computers Lab report 

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Reducing the Model Order of Deep Neural Networks Using Information Theory

May 16, 2016
Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo

* To appear in ISVLSI 2016 special session 

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