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Peter Y. K. Cheung

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Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference

Jan 02, 2022
Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah

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Enabling Binary Neural Network Training on the Edge

Feb 10, 2021
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides

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LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

Oct 24, 2019
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides

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Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs

Oct 21, 2019
Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George Constantinides, Cheng-Zhong Xu

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LUTNet: Rethinking Inference in FPGA Soft Logic

Apr 01, 2019
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides

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Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going

Jan 21, 2019
Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides

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Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic

Jul 17, 2018
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Leong, Peter Y. K. Cheung

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