Cross-Link Interference Mitigation With Over-the-Air Pilot Forwarding for Dynamic TDD

Dynamic time-division duplex (D-TDD) aided mobile communication systems bear the potential to achieve significantly higher spectral efficiency than traditional static TDD based systems. However, strong cross-link interference (CLI) may be caused by different transmission directions between adjacent cells in D-TDD systems, thus degrading the performance. Most existing CLI mitigation schemes require sharing certain information among base stations (BSs) via backhaul links. This strategy is usually expensive and suffers high latency. Alternatively, we propose a pilot information sharing scheme based on over-the-air forwarding of the downlink pilot of the interfering BS to the interfered BS via a wireless terminal, along with a dedicated CLI channel estimation method. Simulation results demonstrate that thanks to the proposed pilot information sharing scheme the classic interference rejection combining (IRC) receiver achieves a signal detection performance highly comparable to that of the IRC detector with perfect pilot information, necessitating no information sharing among BSs via backhaul links. Furthermore, the proposed CLI channel estimation scheme reduces the impact of errors introduced by pilot forwarding, thereby improving the performance of both CLI channel estimation and signal detection.

Amplifier-Enhanced Memristive Massive MIMO Linear Detector Circuit: An Ultra-Energy-Efficient and Robust-to-Conductance-Error Design

The emerging analog matrix computing technology based on memristive crossbar array (MCA) constitutes a revolutionary new computational paradigm applicable to a wide range of domains. Despite the proven applicability of MCA for massive multiple-input multiple-output (MIMO) detection, existing schemes do not take into account the unique characteristics of massive MIMO channel matrix. This oversight makes their computational accuracy highly sensitive to conductance errors of memristive devices, which is unacceptable for massive MIMO receivers. In this paper, we propose an MCA-based circuit design for massive MIMO zero forcing and minimum mean-square error detectors. Unlike the existing MCA-based detectors, we decompose the channel matrix into the product of small-scale and large-scale fading coefficient matrices, thus employing an MCA-based matrix computing module and amplifier circuits to process the two matrices separately. We present two conductance mapping schemes which are crucial but have been overlooked in all prior studies on MCA-based detector circuits. The proposed detector circuit exhibits significantly superior performance to the conventional MCA-based detector circuit, while only incurring negligible additional power consumption. Our proposed detector circuit maintains its advantage in energy efficiency over traditional digital approach by tens to hundreds of times.

In-Memory Massive MIMO Linear Detector Circuit with Extremely High Energy Efficiency and Strong Memristive Conductance Deviation Robustness

The memristive crossbar array (MCA) has been successfully applied to accelerate matrix computations of signal detection in massive multiple-input multiple-output (MIMO) systems. However, the unique property of massive MIMO channel matrix makes the detection performance of existing MCA-based detectors sensitive to conductance deviations of memristive devices, and the conductance deviations are difficult to be avoided. In this paper, we propose an MCA-based detector circuit, which is robust to conductance deviations, to compute massive MIMO zero forcing and minimum mean-square error algorithms. The proposed detector circuit comprises an MCA-based matrix computing module, utilized for processing the small-scale fading coefficient matrix, and amplifier circuits based on operational amplifiers (OAs), utilized for processing the large-scale fading coefficient matrix. We investigate the impacts of the open-loop gain of OAs, conductance mapping scheme, and conductance deviation level on detection performance and demonstrate the performance superiority of the proposed detector circuit over the conventional MCA-based detector circuit. The energy efficiency of the proposed detector circuit surpasses that of a traditional digital processor by several tens to several hundreds of times.