Physics-Informed Structure Anchoring With Capture-Aware Prototype Calibration for Cross-Environment RF Fingerprinting

Radio frequency fingerprint identification (RFFI) exploits transmitter-specific hardware imperfections as physicallayer identity cues for Internet of Things (IoT) devices, but deep models often degrade across acquisition environments. In multi-antenna reception, antenna topology and frequencyoffset dynamics structure receiver observations, while capturedependent variation distorts target embeddings and misaligns source-trained decision boundaries. This article proposes physicsinformed structure anchoring with capture-aware prototype calibration (PISA-CAPC) to address both representation and decision mismatches. The two stages separate source representation construction from target decision correction. During source training, PISA organizes antenna tokens through a topology-guided graph, conditions propagation on CFO-derived acquisition dynamics, and applies bounded contextual residual suppression to preserve identity evidence. At deployment, unlabeled capture-aware prototype calibration (U-CAPC) estimates capture-local prototypes and recalibrates target decision scores while keeping the representation and source classifier fixed. Thus, calibration uses neither target labels nor target-domain backbone updates. On a measured WiFi benchmark with four receive antennas and ten transmitters, PISA-CAPC achieves a mean target-domain Macro-F1 of 0.9257 under a balanced transductive setting. Component ablations support complementary roles for topology-guided anchoring, CFO-conditioned modulation, reliability-aware token aggregation, contextual suppression, and capture-aware calibration. These results indicate that physically motivated representation learning can be combined with labelfree decision calibration to improve cross-environment RFFI under the evaluated protocol without changing the deployed backbone.

FPGA Implementation of Convolutional Neural Network for Real-Time Handwriting Recognition

Machine Learning (ML) has recently been a skyrocketing field in Computer Science. As computer hardware engineers, we are enthusiastic about hardware implementations of popular software ML architectures to optimize their performance, reliability, and resource usage. In this project, we designed a highly-configurable, real-time device for recognizing handwritten letters and digits using an Altera DE1 FPGA Kit. We followed various engineering standards, including IEEE-754 32-bit Floating-Point Standard, Video Graphics Array (VGA) display protocol, Universal Asynchronous Receiver-Transmitter (UART) protocol, and Inter-Integrated Circuit (I2C) protocols to achieve the project goals. These significantly improved our design in compatibility, reusability, and simplicity in verifications. Following these standards, we designed a 32-bit floating-point (FP) instruction set architecture (ISA). We developed a 5-stage RISC processor in System Verilog to manage image processing, matrix multiplications, ML classifications, and user interfaces. Three different ML architectures were implemented and evaluated on our design: Linear Classification (LC), a 784-64-10 fully connected neural network (NN), and a LeNet-like Convolutional Neural Network (CNN) with ReLU activation layers and 36 classes (10 for the digits and 26 for the case-insensitive letters). The training processes were done in Python scripts, and the resulting kernels and weights were stored in hex files and loaded into the FPGA's SRAM units. Convolution, pooling, data management, and various other ML features were guided by firmware in our custom assembly language. This paper documents the high-level design block diagrams, interfaces between each System Verilog module, implementation details of our software and firmware components, and further discussions on potential impacts.