Homodyne vs. Heterodyne Architectures in Sub-THz Transceivers: A Phase Noise Perspective

This letter examines the impact of oscillator phase noise on sub-terahertz OFDM transceiver architectures, with a focus on the comparison between homodyne and heterodyne designs. Using a Hexa-X compliant phase noise model, we analytically show that heterodyne architectures reduce the total accumulated phase noise variance by distributing frequency translation across lower-frequency oscillators under realistic phase-noise scaling laws, thereby shifting the dominant impairment from inter-carrier interference to common phase error. OFDM simulations at 70 GHz and 140 GHz demonstrate that while homodyne architectures remain competitive at mmWave frequencies, heterodyne designs provide improved robustness to phase noise at higher sub-THz carriers. These results highlight transceiver architecture as a key design lever for relaxing oscillator and phase-locked loop constraints in future sub-THz wireless systems.

On the Performance of ISAC over the D-Band in a Phase-Noise Aware OFDM Systems

Phase noise (PN) is a critical impairment at D-band frequencies (110 to 170 GHz), which are widely investigated as promising candidates for beyond 5G/6G ISAC systems. This paper evaluates OFDM based ISAC sensing performance under realistic oscillator impairments using a hardware-tuned 3GPP PN model at 130 GHz and FFT based radar processing. With a numerology of 480 kHz, results show that PN introduces range RMSE floors of 0.04 to 0.05 m and velocity RMSE floors of 0.12 to 0.18 m/s. Doppler sidelobe metrics also saturate, with PSLR around minus 6 dB and ISLR around minus 4 dB. These findings confirm that range accuracy remains bandwidth limited, while velocity estimation and sidelobe suppression are strongly PN-sensitive. The study highlights the importance of PN-aware waveform and numerology design for sub-THz ISAC and provides insights for future multi-band transceivers. Communication metrics and PN mitigation strategies such as PTRS and CPE tracking are left for future work.

Frequency-Dependent Power Consumption Modeling of CMOS Transmitters for WNoC Architectures

Wireless Network-on-Chip (WNoC) systems, which wirelessly interconnect the chips of a computing system, have been proposed as a complement to existing chip-to-chip wired links. However, their feasibility depends on the availability of custom-designed high-speed, tiny, ultra-efficient transceivers. This represents a challenge due to the tradeoffs between bandwidth, area, and energy efficiency that are found as frequency increases, which suggests that there is an optimal frequency region. To aid in the search for such an optimal design point, this paper presents a behavioral model that quantifies the expected power consumption of oscillators, mixers, and power amplifiers as a function of frequency. The model is built on extensive surveys of the respective sub-blocks, all based on experimental data. By putting together the models of the three sub-blocks, a comprehensive power model is obtained, which will aid in selecting the optimal operating frequency for WNoC systems.