Enhancing Co-packaging Optics Enabled Silicon Photonics Security Assurance Hardware Fingerprinting

Silicon photonics enables integration of optical components using standard semiconductor processes, greatly improving data communication bandwidth and energy efficiency. However, photonics integrated circuits (PICs) face unique security challenges, such as counterfeit or tampering threats, that conventional electronic security methods do not address. We propose a novel hardware fingerprinting technique that embeds two dimensional photonic crystal patterns into the density control filler regions of a PIC. Each PhC pattern is designed to resonate a specific visible to near infrared wavelengths, producing a distinctive optical signature (based on wavelength, polarization, and incident angle) for each device. Finite difference time domain (FDTD) simulation using ANSYS Lumerical is employed to optimize nanostructure dimensions and spacing so that each device's reflection/absorption spectrum contains unique narrowband peaks. No extra fabrication steps or materials are required beyond standard lithography, keeping costs low. The embedded nanostructures have sub-50nm precision, making forgery extremely difficult. Our method yields a high resolution, scalable fingerprint for silicon photonic chips, enabling cost-effective device authentication and improved supply chain security.

Design Guidelines for In-line X-ray Inspection in Advanced Packaging Technology: A CoWoS Case Study

The shift towards advanced packaging technologies, including 2.5D and 3D integration, addresses the limitations of traditional methods while meeting increasing demands for performance, miniaturization, and efficiency. These methods enhance functionality and support heterogeneous integration but also introduce metrology challenges due to complex, three-dimensional structures. X-ray imaging, crucial for nondestructive inspection, faces compatibility issues such as material density similarities and noise scattering. To address these challenges, we propose a framework based on AI-integrated Design of Experiment (DoE) to develop design guidelines to optimize X-ray compatibility during the design stage. This framework, demonstrated through a case study on Chip-on-Wafer-on-Substrate (CoWoS) packaging, systematically analyzes design parameters and material properties to develop guidelines for improved inspection accuracy. Our method integrates AI to predict outcomes and optimize processes, ensuring high-quality X-ray images and enhancing defect detection. Implementing these guidelines can significantly improve inspection accuracy and reliability, reducing production costs and supporting the efficiency and scalability of advanced semiconductor technologies.

Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging

As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeiting, and supply chain infiltration. This paper presents Nanoelectromechanical Systems (NEMS) as an emerging class of hardware security primitives that enable physical assurance, tamper detection, and authentication at the device level. Leveraging mechanisms such as NEMS-based Physically Unclonable Functions (PUFs), shape memory materials, resonance-based fingerprints, and physical unlocking architectures, these systems offer enhanced resilience to reverse engineering, side-channel attacks, and environmental degradation. By harnessing mechanical unpredictability and fabrication-induced nanoscale variability, NEMS technologies introduce a physically robust and low-power alternative to conventional digital security methods. Their seamless integration into standard semiconductor workflows paves the way for scalable, verifiable, and secure solutions across defense, aerospace, critical infrastructure, and consumer electronics.

Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration

Failure analysis is being reshaped by heterogeneous integration, chiplet-based architectures, hybrid bonding, backside technologies, & increasingly buried package structures. To examine how practitioners view this transition, an anonymous survey was distributed across a broad set of organizations involved in semiconductor design, packaging, systems, tools, & failure analysis. The survey collected approximately one hundred responses & probed organizational background, supported product domains, future priorities in failure analysis, critical bottlenecks, sample preparation challenges, emerging architecture specific pain points, & perceived needs for workflow acceleration & data standardization. The results show that heterogeneous integration, chiplet, and three-dimensional products dominate the respondent base at 69%, while package & heterogeneous integration failure analysis received the highest importance rating at 7.92 out of 10. Hybrid bonding emerged as the most difficult new architecture to analyze at 54%, higher-resolution non-destructive imaging ranked as the most important future accelerator at 8.18 out of 10, and 83% of respondents supported formalized data standardization frameworks. The complete survey data are provided in Appendix A (Table II) to improve transparency & support future benchmarking.