A Practical Analysis: Understanding Phase Noise Modelling in Time and Frequency Domain for Phase-Locked Loops

In MIMO systems, the presence of phase noise is a significant factor that can degrade performance. For MIMO testbeds build from SDR devices, phase noise cannot be ignored, particular in applications that require phase synchronization. This is especially relevant in MIMO systems that employ digital beamforming, where precise phase alignment is crucial. Accordingly, accurate phase noise modelling of SDR devices is essential. However, the information provided in data sheets for different SDR models varies widely and is often insufficient for comprehensive characterization of their phase noise performance. While numerical simulations of PLL phase noise behavior are documented in the literature, there is a lack of extensive measurements supported by appropriate system modelling. In this work, we present a practical phase noise modeling methodology applied to an SDR from the USRP X310 series. Based on measurement data, we derive estimates of key PLL performance indicators such as cycle-to-cycle jitter, oscillator constants, and PLL bandwidth. Furthermore, we propose a parametric model for the phase noise PSD of the PLL circuit and provide corresponding parameter estimates. This model can be used for further investigation into the impact of phase noise on MIMO system performance implemented by similar SDR devices.