D-Band 2D MIMO FMCW Radar System Design for Indoor Wireless Sensing

In this article, we present system design of D-band multi-input multi-output (MIMO) frequency-modulated continuous-wave (FMCW) radar for indoor wireless sensing. A uniform rectangular array (URA) of radar elements is used for 2D direction-of-arrival (DOA) estimation. The DOA estimation accuracy of the MIMO radar array in the presence of noise is evaluated using the multiple-signal classification (MUSIC) and the minimum variance distortionless response (MVDR) algorithms. We investigate different scaling scenarios for the radar receiver (RX) SNR and the transmitter (TX) output power with the target distance. The DOA estimation algorithm providing the highest accuracy and shortest simulation time is shown to depend on the size of the radar array. Specifically, for a 64-element array, the MUSIC achieves lower root-mean-square error (RMSE) compared to the MVDR across 1--10\,m indoor distances and 0--30\,dB SNR (e.g., $\rm 0.8^{\circ}$/$\rm 0.3^{\circ}$ versus $\rm 1.0^{\circ}$/$\rm 0.5^{\circ}$ at 10/20\,dB SNR and 5\,m distance) and 0.5x simulation time. For a 16-element array, the two algorithms provide comparable performance, while for a 4-element array, the MVDR outperforms the MUSIC by a large margin (e.g., $\rm 8.3^{\circ}$/$\rm 3.8^{\circ}$ versus $\rm 62.2^{\circ}$/$\rm 48.8^{\circ}$ at 10/20\,dB SNR and 5\,m distance) and 0.8x simulation time. Furthermore, the TX output power requirement of the radar array is investigated in free-space and through-wall wireless sensing scenarios, and is benchmarked by the state-of-the-art D-band on-chip radars.

A Dual-Band 28/38-GHz Power Amplifier With Inter-Band Suppression in 22-nm FD-SOI CMOS for Multi-Standard mm-Wave 5G Communications

In this article, we present a dual-band 28/38-GHz power amplifier (PA) with inter-band suppression for millimeter-wave 5G communications. The dual-band operation is achieved using a center-tapped transformer network with an extra resonator which can provide optimum load impedance of the transistor in the two bands and synthesize a short-circuit between the two bands. This feature suppresses the PA signal emissions in the inter band, commonly allocated for other applications. A design procedure is developed for the proposed matching network including physical limits on the quality factor and the coupling coefficient of the transformer. The PA is designed using a 22-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process. The transistor stacking and a four-path transformer parallel-series power combining techniques are used to achieve high output power using the low-voltage process. The PA achieves simulated performance of 22.6/22.0 dBm saturated output power, 19.8/20.0 dBm output power at 1-dB gain compression, and 33/32 % maximum power-added efficiency (PAE) at 28/38 GHz. The inter-band suppression is 6 dB at 33 GHz.