Picture for Maryam Mirsadeghi

Maryam Mirsadeghi

An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

Add code
Mar 17, 2026
Viaarxiv icon

Spiking neural networks trained via proxy

Add code
Sep 27, 2021
Figure 1 for Spiking neural networks trained via proxy
Figure 2 for Spiking neural networks trained via proxy
Figure 3 for Spiking neural networks trained via proxy
Figure 4 for Spiking neural networks trained via proxy
Viaarxiv icon

Spike time displacement based error backpropagation in convolutional spiking neural networks

Add code
Aug 31, 2021
Figure 1 for Spike time displacement based error backpropagation in convolutional spiking neural networks
Figure 2 for Spike time displacement based error backpropagation in convolutional spiking neural networks
Figure 3 for Spike time displacement based error backpropagation in convolutional spiking neural networks
Figure 4 for Spike time displacement based error backpropagation in convolutional spiking neural networks
Viaarxiv icon

BS4NN: Binarized Spiking Neural Networks with Temporal Coding and Learning

Add code
Jul 08, 2020
Figure 1 for BS4NN: Binarized Spiking Neural Networks with Temporal Coding and Learning
Figure 2 for BS4NN: Binarized Spiking Neural Networks with Temporal Coding and Learning
Figure 3 for BS4NN: Binarized Spiking Neural Networks with Temporal Coding and Learning
Figure 4 for BS4NN: Binarized Spiking Neural Networks with Temporal Coding and Learning
Viaarxiv icon