A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning

This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications.

A 125$μ$W 8kS/s Sub-pA Area-Efficient Current Sensing 45nm CMOS ADC for Biosensing

This paper presents a 125$\mu$W, area efficient (0.042mm2) 81dB DR, 8kS/s current sensing ADC in 45nm CMOS capable of sensing sub-pA currents. Our approach combines the transimpedance amplifier (TIA) and ADC into a unified structure by folding a low-noise capacitive TIA into the first stage integrator of a 2nd order Delta-Sigma modulator. The dominant DAC feedback noise is mitigated by utilizing current scaling via slope modification by an integrator and differentiator pair.