Introduction to Non-Invasive Current Estimation (NICE)

It is notoriously difficult to measure instantaneous supply current to a device such as an ASIC, FPGA, or CPU without also affecting the instantaneous supply voltage and compromising the operation of the device [21]. For decades designers have relied on rough estimates of dynamic load currents that stimulate a designed Power Delivery Network (PDN). The consequences of inaccurate load-current characterization can range from excessive PDN cost and lengthened development schedules to poor performance or functional failure. This paper will introduce and describe a method to precisely determine timedomain current waveforms from a pair of measured timedomain voltage waveforms. This NonInvasive Current Estimation (NICE) method is based on established twoport network theory along with component and board modeling techniques that have been validated through measurements on demonstrative circuits. This paper will show that the NICE method works for any transient event that can be captured on a digital oscilloscope. Limitations of the method and underlying measurements are noted where appropriate. The method is applied to a simple PDN with an arbitrary load, and the NICE-derived current waveform is verified against an independent measurement by sense resistor. With careful component and board modeling, it is possible to calculate current waveforms with a root mean square error of less than five percent compared to the reference measurement. Current transients that were previously difficult or impossible to characterize by any means can now be calculated and displayed within seconds of an oscilloscope-trigger event by using NICE. ASIC and FPGA manufacturers can now compute the startup current for their device and publish the actual waveform, or provide a piecewiselinear SPICE model (PWL source) to facilitate design and testing of the regulator and PDN required to support their device.

Comparison of Optical and Electrical Links for Highly-Interconnected Systems

As data rates for multi-gigabit serial interfaces within multi-node compute systems approach and exceed 10 Gigabits per second (Gbps), board-to-board and chip-to-chip optical signaling solutions become more attractive, particularly for longer (e.g. 50-100 cm) links. The transition to optical signaling will potentially allow new high performance compute (HPC) system architectures that benefit from characteristics unique to optical links. To examine these characteristics, we built and tested several optical demonstration vehicles; one based on dense wavelength division multiplexing (DWDM), and others based on multiple point-to-point links carried across multimode fibers. All test vehicles were constructed to evaluate applicability to a multi-node compute system. Test results, combined with data from recent research efforts are summarized and compared to equivalent electrical links and the advantages and design characteristics unique to optical signaling are identified.

PWB Manufacturing Variability Effects on High Speed SerDes Links: Statistical Insights from Thousands of 4-Port SParameter Measurements

Variability analysis is important in successfully deploying multi-gigabit backplane printed wiring boards (PWBs) with growing numbers of high-speed SerDes links. We discuss the need for large sample sizes to obtain accurate variability estimates of SI metrics (eye height, phase skew, etc). Using a dataset of 11,961 S-parameters, we demonstrate statistical techniques to extract accurate estimates of PWB SI performance variations. We cite numerical examples illustrating how these variations may contribute to underestimated or overestimated design criteria, causing unnecessary design expense. Tabular summaries of performance variation and key findings of broad interest to the general SI community are highlighted.

High Speed Parallel Signal Crosstalk Cancellation Concept

High performance computing (HPC) systems make extensive use of high speed electrical interconnects, in routing signals among processing elements, or between processing elements and memory. Increasing bandwidth demands result in high density, parallel I/O exposed to crosstalk due to tightly coupled transmission lines. The crosstalk cancellation signaling concept discussed in this paper utilizes the known, predictable theory of coupled transmission lines to cancel crosstalk from neighboring traces with carefully chosen resistive cross-terminations between them. Through simulation and analysis of practical bus architectures, we explore the merits of crosstalk cancellation which could be used in dense interconnect HPC (or other) applications.

Applications of Optimization Routines in Signal Integrity Analysis

Signal integrity analysis often involves the development of design guidelines through manual manipulation of circuit parameters and judicious interpretation of results. Such an approach can result in significant effort and sub-optimal conclusions. Optimization routines have been well proven to aid analysis across a variety of common tasks. In addition, there are several non-traditional applications where optimization can be useful. This paper begins by describing the basics of optimization followed by two specific case studies where non-traditional optimization provides significant improvements in both analysis efficiency and channel performance.