IO Pad Integrity in Energy-Efficient Neuromorphic Chips

Neuromorphic computing relies on low-power, high-reliability hardware, yet the integrity of input/output pads (IOPADs) remains an underexplored factor affecting system performance. This chapter examines the role of IOPAD integrity in neuromorphic VLSI design and connects algorithmic development with practical hardware implementation. While much attention has been given to spiking neural networks (SNNs) and ultra-low-power core logic, the electrical and functional robustness of the I/O interface is equally critical for ensuring signal fidelity and minimizing energy consumption. We review the structure and function of IOPADs, outline their influence on power, performance, and reliability, and discuss design trade-offs involving pad libraries, pad ring architectures, and bonding strategies. The chapter also introduces the fundamentals of SNNs and summarizes the digital hardware design flow from behavioral description to physical layout. Physical implementation considerations are highlighted using the SkyWater 130 nm CMOS process as a practical platform for neuromorphic prototyping. Real-world examples illustrate how early-stage I/O planning can prevent redesign, reduce yield loss, and improve overall system efficiency. This work emphasizes that IOPAD integrity is a key enabler of scalable, energy-efficient neuromorphic systems.

MAC Performance and Algorithmic Optimization in Matrix Multiplication Workloads

Matrix multiplication is a fundamental computational kernel underlying a wide range of real-world applications, including machine learning, scientific computing, signal processing, and computer graphics. Its performance directly impacts the efficiency, scalability, and energy consumption of modern computing systems. This paper presents a comparative analysis of several matrix multiplication algorithms implemented in software and examined in the context of their hardware execution characteristics. Naive, NumPy, Strassen, and Winograd algorithms are evaluated based on execution time, user time, and CPU time across increasing matrix sizes. The performance metrics reveal computational bottlenecks and highlight the benefits of algorithmic optimizations. Furthermore, the study investigates the mathematical operations underlying each algorithm and analyzes how matrix dimensions influence MAC (Multiply-Accumulate) behavior and overall computational efficiency in the hardware domain. The results provide a performance benchmark and contribute to understanding how algorithmic choices interact with modern computing architectures for applications in computer architecture, data science, and real-time embedded systems.

HiLTS: Human in the Loop Therapeutic System: A Wireless-enabled Precision Medicine Platform for Brainwave Entrainment

Epileptic seizures arise from abnormally synchronised neural activity and remain a major global health challenge, affecting more than 50 million people worldwide. Despite advances in pharmacological interventions, a significant proportion of patients continue to experience uncontrolled seizures, underscoring the need for alternative neuromodulation strategies. Rhythmic neural entrainment has recently emerged as a promising mechanism for disrupting pathological synchrony, but most existing systems rely on complex analogue electronics or high-power stimulation hardware. This study investigates a minimal digital custom-designed chip that generates a stable 6 Hz oscillation capable of entraining epileptic seizure activity. Using a publicly available EEG seizure dataset, we extracted and averaged analogue seizure waveforms, digitised them to emulate neural front-ends, and directly interfaced the digitised signals with digital output recordings acquired from the chip using a Saleae Logic analyser. The chip pulse train was resampled and low-pass-reconstructed to produce an analogue 6 Hz waveform, allowing direct comparison between seizure morphology, its digitised representation, and the entrained output. Frequency-domain and time-domain analyses demonstrate that the chip imposes a narrow-band 6 Hz rhythm that overrides the broadband spectral profile of seizure activity. These results provide a proof-of-concept for low-power digital custom-designed entrainment as a potential pathway toward simplified, wearable seizure-interruption devices for precision medicine and future healthcare devices.

Hardware/Software Co-Design for Spike Based Recognition

The practical applications based on recurrent spiking neurons are limited due to their non-trivial learning algorithms. The temporal nature of spiking neurons is more favorable for hardware implementation where signals can be represented in binary form and communication can be done through the use of spikes. This work investigates the potential of recurrent spiking neurons implementations on reconfigurable platforms and their applicability in temporal based applications. A theoretical framework of reservoir computing is investigated for hardware/software implementation. In this framework, only readout neurons are trained which overcomes the burden of training at the network level. These recurrent neural networks are termed as microcircuits which are viewed as basic computational units in cortical computation. This paper investigates the potential of recurrent neural reservoirs and presents a novel hardware/software strategy for their implementation on FPGAs. The design is implemented and the functionality is tested in the context of speech recognition application.