Alert button
Picture for Xinheng Liu

Xinheng Liu

Alert button

HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation

Jul 22, 2022
Yao Chen, Junhao Pan, Xinheng Liu, Jinjun Xiong, Deming Chen

Figure 1 for HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
Figure 2 for HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
Figure 3 for HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
Figure 4 for HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
Viaarxiv icon

HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation

Dec 28, 2021
Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, Deming Chen

Figure 1 for HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Figure 2 for HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Figure 3 for HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Figure 4 for HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Viaarxiv icon

WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs

Jul 09, 2021
Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen

Figure 1 for WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
Figure 2 for WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
Figure 3 for WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
Figure 4 for WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
Viaarxiv icon

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations

Dec 22, 2020
Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang

Figure 1 for FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Figure 2 for FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Figure 3 for FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Figure 4 for FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Viaarxiv icon

EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions

May 06, 2020
Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-mei Hwu, Deming Chen

Figure 1 for EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
Figure 2 for EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
Figure 3 for EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
Figure 4 for EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
Viaarxiv icon

NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving

Nov 18, 2019
Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-mei Hwu, Junli Gu, Deming Chen

Figure 1 for NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
Figure 2 for NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
Figure 3 for NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
Figure 4 for NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
Viaarxiv icon

Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs

Mar 23, 2018
Chuanhao Zhuge, Xinheng Liu, Xiaofan Zhang, Sudeep Gummadi, Jinjun Xiong, Deming Chen

Figure 1 for Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Figure 2 for Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Figure 3 for Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Figure 4 for Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Viaarxiv icon