Alert button
Picture for Qiuwen Lou

Qiuwen Lou

Alert button

Super Efficient Neural Network for Compression Artifacts Reduction and Super Resolution

Jan 26, 2024
Wen Ma, Qiuwen Lou, Arman Kazemi, Julian Faraone, Tariq Afzal

Viaarxiv icon

Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators

Oct 31, 2019
Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, Xiaobo Sharon Hu, Yiyu Shi

Figure 1 for Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Figure 2 for Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Figure 3 for Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Figure 4 for Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Viaarxiv icon

Nonvolatile Spintronic Memory Cells for Neural Networks

May 29, 2019
Andrew W. Stephan, Qiuwen Lou, Michael Niemier, X. Sharon Hu, Steven J. Koester

Figure 1 for Nonvolatile Spintronic Memory Cells for Neural Networks
Figure 2 for Nonvolatile Spintronic Memory Cells for Neural Networks
Figure 3 for Nonvolatile Spintronic Memory Cells for Neural Networks
Figure 4 for Nonvolatile Spintronic Memory Cells for Neural Networks
Viaarxiv icon

Application-level Studies of Cellular Neural Network-based Hardware Accelerators

Feb 28, 2019
Qiuwen Lou, Indranil Palit, Tang Li, Andras Horvath, Michael Niemier, X. Sharon Hu

Figure 1 for Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Figure 2 for Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Figure 3 for Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Figure 4 for Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Viaarxiv icon

Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA

Oct 25, 2018
Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen

Figure 1 for Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Figure 2 for Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Figure 3 for Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Figure 4 for Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Viaarxiv icon